#CISC

[assembly-official]

Cisc: complex instruction set computer

I get such a kick out of the prefix 'cis'

getting a book cislated: yup, still can't read it

cisition timeline: just a selfie

cisformation: make a bunch of super saiyan sounds and walk away

cisubstantiation: by the power of god this bread has remained bread

idk its just neat

[berita-bola-terupdate-2024]

Gokilnya Roaring Night Chelsea vs Manchester United Bareng CISC Jakarta: Bikin Merinding!

[saiita]

6、计算机体系结构分类

1、flynn分类 体系结构类型结构关键特性代表单指令流数据流SISD控制部分：1个处理器：1个主存模块：1个单处理器系统单指令流多数据流SIMD控制部分：1个处理器：多个主存模块：多个各处理器以异步的形式执行同一条指令并行处理机阵列处理机超级向量处理机多指令流单数据流MISD控制部分：多个处理器：1个主存模块：多个被证明不可能，至少是不实际目前没有文献称流水线计算机为此类多指令流多数据流MIMD控制部分：多个处理器：多个主存模块：多个能够实现作业、任务、指令等各级全面并行多处理机系统多计算机 例题：Flynn分类法根据计算机在执行程序的过程中（A）的不同组合，将计算机分为4类。当前主流的多核计算机属于（D）计算机 A.指令流和数据流 B.数据流和控制流 C.指令流和控制流 D.数据流和总线带宽 A.SISD B.SIMD C.MISD…

[nerdwelt]

Die britische Luftwaffe bewacht Island während des Europaratsgipfels

OSLO, 14. Mai (Reuters) – Die isländische Regierung gab am Sonntag bekannt, dass nächste Woche ein Geschwader der britischen Luftwaffe den Himmel über dem nordischen Land patrouillieren wird, während sich Staats- und Regierungschefs aus ganz Europa in Reykjavik treffen, um die Sicherheit des Kontinents und die Unterstützung der Ukraine zu besprechen. Das von den beiden Ländern am 15. und 19. Mai…

[metbuat]

Putin müharibəni Rusiyanın yaşaması uğrunda döyüş kimi təqdim edir

MOSKVA, 26 fevral (Reuters) – Prezident Vladimir Putin Ukrayna müharibəsi ilə bağlı Qərblə qarşıdurmanı Rusiya və rus xalqının yaşaması üçün ekzistensial döyüş kimi qiymətləndirdi və NATO-nun nüvə imkanlarını nəzərə almağa məcbur olduğunu söylədi. Ukraynanın işğalı ilə bağlı göstəriş verəndən bir il sonra Putin getdikcə müharibəni Rusiya tarixinin bir anı kimi təqdim edir və Rusiyanın və onun…

[usdailyeu]

[USNews] Ukraine steps up diplomacy amid fighting, power outages

[USNews] Ukraine steps up diplomacy amid fighting, power outages

Zelenskiy talks to leaders of U.S., France, Turkey Ukraine battling to restore power to Odesa, other areas U.S. support to continue ‘for as long as it takes’ – Yellen KYIV, Dec 12 (Reuters) – The United States is prioritising efforts to boost Ukraine’s air defences, President Joe Biden told his Ukrainian counterpart on Sunday, as President Volodymyr Zelenskiy stepped up efforts to secure…

[andmaybegayer]

So, if you casually search for the answer to this you unfortunately mostly get platitudes and horseshit. I am not an experienced processor designer so I can only offer you one step up from platitudes and horseshit. With that said:

The basic processor you learn about in school is a very simple machine, the idea is that you have memory somewhere, and at t=0 you start reading the first instruction in memory, do what it tells you to do, and then the next one, and then the next one. Sometimes an instruction will tell you to read a value out of memory, or write a new one into memory, or jump the execution to a new point, or do something with the values you've been manipulating.

x86 and ARM represent Complex and Reduced Instruction Set Computing respectively, CISC and RISC. RISC and CISC are somewhat distinguished by how many instructions they have, with RISC generally having simple, composable instructions, whereas CISC has more, special-purpose instructions, especially when you count "mandatory" or "core" instructions.

These are not hard-and-fast categories but for all but the most niche architectures most people agree on which are which, for reasons which might become apparent if I do a good job here.

Most instruction sets, even RISC ones, have a ton of performance-enhancing extensions that can operate on wide vectors and do other accelerated operations, so the overall instruction counts can be closer than you'd expect. There are still noticeable differences though, for example, a minimal ARM processor has to implement a couple hundred instructions, while a minimal x64 processor has to implement well over a thousand. A minimal to-spec RISC-V32 processor has only 47 base instructions.

In your toy baby processor, you execute one instruction at a time. The school version of this is the Fetch/Decode/Execute/Store cycle. You fetch an instruction from memory, decode it, execute it in your logic units, and then store back the results. In practice what this means is that at any moment, three of the four major components of your system are sitting idle, so we start pipelining. While one instruction is being executed, the one after it can be decoded, and the one after that can be fetched. If it turns out that the execution of the current instruction requires a new instruction to be executed, we stall the pipeline until we catch up, losing some performance in the moment but still gaining overall.

This is a good start, but there's another issue, which is that individual instructions do not all take the same amount of time to execute. CISC systems often begin with a dream of having really, really fast useful instructions that can be deployed by just using the right instruction call, you know, oh this popular encryption method uses an operation where we fold a number back on itself eight times and XOR it, so let's just do that in hardware. You can also think of it as a way to shrink code, if you have a microcontroller that can do a multi-step operation in one instruction.

Unfortunately very quickly you run up against limitations: implementing hardware logic for all your thousands of instructions uses up valuable silicon space, and a bigger chip is more expensive for several reasons (greater susceptibility to flaws and errors, lower yield per wafer, etc.)

So we do microcode. Microcode is when your processor contains a second, secret processor to do the actual work. When an instruction like "fold a number and XOR it" it comes along, a smaller, simpler processor that is maybe more like a pile of state machines and ALU's can be manipulated by a hypervisor built into the chip to execute the effective results of the intended instructions in a couple of cycles, generally (but not always) faster than a naive implementation but much slower than dedicated hardware.

If you want to know more about microcode, check out this C3 talk that goes into great detail about the x86 microcode, especially the front half.

This is slower than if you had huge expensive dedicated hardware, but you can shrink your dies to resuse hardware for multiple operations, and you can now pipeline microarchitecture-based operations to try and make up for it, squeezing multiple operations into your multi-purpose hardware. Intel started using microcode-like designs with the P6 architecture in the mid-90's, I mentioned this in my list of cool chips:

This has some weaknesses though. If your CISC instructions are too complicated, they can start to become highly non-deterministic, they can take multiple cycles to execute, and now you need to dedicate a lot of processor design and effort to optimizing the pipelining and microarchitecture of these instructions to make more efficient use of your limited silicon. You leave yourself open to weird stalling and wasted compute cycles, and you spend a lot of silicon tracking all of this state and shuffling microoperations to try and make them run smoothly. Eventually you're spending so much silicon on managing microarchitecture that you lose any of the benefits you got by doing it

RISC systems generally don't do microcode in the conventional sense, because their instructions are so limited that you can kind of (do not say this to a processor designer) think of them as being microcode already. You compose the operations together into the end result you want at compile-time, rather than fussing around with stupendously complicated CPU designs.

Because of this, the individual instructions are much more deterministic and break down into pipelineable operations much more cleanly, so when combined with your compile-time optimizations you don't have as much work to do at runtime, you can use relatively simple pipelines and still get high utilization and lower waste on less silicon.

The end result is that you can shrink your silicon, reduce your complexity, while still maintaining performance parity with the CISC processors, because you're both doing the same kind of thing. Less silicon and higher utilization means better performance within a smaller power envelope, you physically have fewer transistors to switch and they're not being left idle for as long.

So why didn't we just start with RISC? Well, historical reasons mostly I think. CISC makes programming in assembly easy, because it hands the programmer nice "functions" built right into the silicon, and it trims program size by packing long operations into a single instruction. CISC comes from an era where optimizing your CPU to make assembly optimization easier and shaving some bytes off code by packing operations together made sense, and that wasn't the best idea. This article roughly agrees with me

Okay, so far I think most of this is pretty rock solid. This is where I talk out of my ass for a bit: The way I think about this is as the benefit of having insight into the purpose of code up and down the execution stack.

In CISC, you write some code, and your optimizing compiler will assemble it as best as it can to use these really big instructions. Those then get executed onto a CPU that has no idea what that code was, and why it is laid out this way. Your CPU now has to try and use lookahead and other tricks to just guess what you were trying to do, and then pipeline the microoperations that make up your compiled code. If it guesses wrong, the pipeline stalls, stuff has to bubble through, branches fall apart, and you waste a bunch of time computing microoperations that were unnecessary.

In a RISC, you do a lot of this ahead of time. You write your code, and your optimizing compiler can strip out huge chunks of your operations at compile time, if it determines that half of those "microoperations (not that)" are not actually needed. It knows where return values end up, what gets written to memory, and so on. When the code gets to the CPU, it has already been corralled into a nice format for the CPU, which you know a fair amount about, you know what instructions it has, you know how it pipelines because your instructions are simpler, so you can feed it really nice easy to optimize code, and it has a pretty good idea about what all those instructions do because they're very simple, if it didn't need to do them they would have been stripped out at compile-time, and it can focus on just executing what it does get very efficiently.

The result of this is that RISCs are very popular in the modern day, where compilers are good, no one really writes much assembly, and a few dozen extra kilobytes of instructions in a program is fine. You can save power and silicon space while still getting high performance by optimizing your pipelining with simpler operations that increase processor utilization without requiring complex babysitting hardware to oversee the pipeline.

I don't mind Apple products and the various tradeoffs that come with them, but if you hate them, I have good news for you. The reviews are coming in and at long last it seems like Qualcomm is making chips that can actually stand their ground against Apple's: if you get a laptop with a Snapdragon X Pro/Elite chip in you'll finally get the performance + ludicrous battery life that the Apple people have been lording over you since 2020.

[piratesexmachine420]

I love that Intel and AMD still have to keeping dragging the x87 instruction set forwards in this day and age. If anyone proposed it today they'd be laughed out of the city. Having to treat your own processor like a foreign stack-machine accelerator only capable of interacting via DMA is insane. It made sense, yes, when the 8087 was a foreign stack-machine accelerator only capable of interacting via DMA, but since the i486DX in 1989 this has been obsolete. But processors still have to support it!

Even the most modern x64 processors, with the highest core counts and IPCs, are configured on startup to perform a shadow-play with themselves. They have to lie to you, have to pretend that the ST(x) and Rxx registers can't see each-other, that the integer ALU and the floating-point ALU aren't side-by-side on the same chip, that it's still 1978, still a world where BCD is important, still a world before IEEE 754.

Sure, processors still start in real mode, but that hasn't been relevant to user programs in decades. User code doesn't get to touch real mode.

But x87? The x87 instruction set lasted through the i386. It made it to the introduction of protected mode, of privilege rings, of usermode. And so, forever codified in the System V Application Binary Interface, AMD64 Architecture Processor Supplement, every program must begin in x87 mode. Likewise for Windows.

The OS can't save you from history here. You have to choose. It's on you to enter MMX mode, or to use SSE2+ instructions. You can live in the present, if you decide to. But x87 is still there. Still in the background. Still doing its own stupid thing. You can never be sure exactly which extensions you can rely on being present. Except x87. You can always rely on your computer's ability to lie to itself about its abilities.

x87 will outlive us all. Ass-backward forever.

[reportwire]

Analysis: Putin's nuclear treaty move raises stakes over China's growing arsenal

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[ailurinae]

TY!

Not to defend implicit operand sizes but a defense of AT&T syntax I truly don't get is that it not having implicit sizes is good and makes for better code like look if you're writing like, 8086 and you say

mov ax,bx

obviously it's going to be a word? There's no other size it could be?

in general you're not going to have a lot of mixups regarding operand size its not a huge concern...

[lost-my-sanity1]

where's my gonna get disowned soon gang?

[shankhachil]

Oersted’s experiment on the magnetic effect of electric current; magnetic field (B) and field lines due to current in a straight wire (qualitative only); Right Hand Thumb Rule – magnetic field due to a current in a loop; Electromagnets: their uses; comparisons with a permanent magnet; conductor carrying current in a magnetic field experiences a force, Fleming’s Left Hand Rule, and its understanding, Simple introduction to electromagnetic induction; a magnet moved along the axis of a solenoid induces current, Fleming’s Right Hand Rule and its application in understanding the direction of current in a coil and Lenz’s law. Comparison of AC and DC.

Solenoid in part a is not there only the one in electromagnetic induction is..

Oo okay okay I understand

[schoolsofdehradun]

[nerdwelt]

Der Kreml behauptet, dass Russland sich in die von Lügnern erfundenen Wahlen in der Türkei einmischt

MOSKAU, 12. Mai (Reuters) – Der Kreml sagte am Freitag, dass die Behauptungen über die Einmischung Russlands in die bevorstehenden Präsidentschaftswahlen in der Türkei falsch seien und von Lügnern erfunden worden seien. Kemal Kilicdaroglu, der Hauptrivale des türkischen Präsidenten Tayyip Erdogan, richtete am Donnerstag eine Warnung an Russland und beschuldigte Russland, vor der Stichwahl am…

[metbuat]

Frank danışıqları və məyusluq: ABŞ Abrams tanklarına necə bəli oldu

VAŞİNQTON, 26 yanvar (Reuters) – Onlar bahalıdır və onlara qulluq etmək çətindir. Onlar təyyarə yanacağı ilə işləyirlər. Və onları idarə etmək çətindir. ABŞ Pentaqonu Abrams-ın – ən qabaqcıl döyüş tanklarının – Ukraynaya göndərilməsinə qarşı açıq və özəl olaraq ən yaxşı arqumentlərini təqdim etdi. Lakin prezident Joe Biden sonda çərşənbə günü 31 tankın təhvil verilməsini təsdiqləməyə qərar verdi,…

[mysterioushimachal]

Bishop Cotton School, Shimla: A Legacy of Tradition, Excellence, and Innovation